知識力

❒ The larger wafer size the better
The wafer size refers to the diameter of a wafer. Currently, the diameter of Si wafer has been developed from early 6” and 8” to now 12” and even 18” in the future. Si wafer should be subjected to photolithography, doping, etching, thin film growth processes repeatedly, and the result turns out to be like the picture shown in Fig. 1. The Si wafer will be spread with squares with side length of about 5mm, called “die.” Each die has millions of CMOS thereon. Each of the dies are exactly the same. Finally, these square dies will be sliced to obtain a lot of identical chips. After packaging and testing, each die becomes the final product, i.e. Integrated Circuit (IC). 
 

 
Figure 1: Size and yield rate of wafer.
 

In other words, one Si wafer may produce hundreds or thousands of identical chips. Therefore, if the wafer size becomes larger, there will be more chips produced at one time and the “unit cost” for each chip will become lower. The foundry utilizes such a technique for mass production to reduce the cost. Obviously, the larger the wafer size will be the better!

Isn’t that the larger wafer size will also increase the production cost? Indeed, the production cost will become higher if the wafer size gets larger. For example, the production cost of 12” wafer is about twice of 6” wafer. However, the area of 12” wafer is four times of 6” wafer (twice of side length, four times of area), so the outcome number of chips will be four times, so will be the revenue. Obviously, it is profitable, so the foundry is unavoidable to produce 12” wafers.
 
【Remark】
 “Die” and “Chip” are exactly the same thing. Normally, we call the squares before wafer slicing as “dies,” and the squares after wafer slicing as “chips”.
 
❒ The smaller chip size the better
Chip size refers to the size of each chip on the wafer. There are two factors affecting the chip size:
➤ Line width of CMOS: Line width of CMOS means the length of gate, which was from the early 0.35μm, 0.25μm, 0.18μm and 0.13μm to current 90nm, 65nm, 45nm, 22nm and 10nm. The smaller line width means the chip area having the same number of CMOS may be smaller and the number of chips each wafer may produce become more and thus the profit will be higher.
➤ CMOS number within chip: There will be different number of CMOS on a chip according to different functions. For example, the chip for a network card may have 10 million of CMOS, the northbridge chip may have 100 million of CMOS, and the CPU may have 1 billion of CMOS. Once the CMOS number within a chip became more, the structure of the chip will be more complicated, i.e. its unit price may be higher and thus the profit may be higher. If an IC design house could design a chip with more complicated structure, like CPU, it usually means the IC design house possesses excellent technical capability and better competitiveness and should be able to make profits; however, it might also means the technical capability of this design house is worse, so the other company might only take one million of CMOS to produce the chip for network card, but this design house needs five millions of CMOS to implement the same chip. Therefore, we must be very careful when we need to judge the value for IC design house.
 
❒ Bond pad
In Fig. 1, each square chip has been enlarged, so we may see many protruded metal contacts distributed around the chip surface, called “Bond pad.” The structure of Si wafer has been described as having millions of CMOS in the basement; then, producing multiple layers of metal wires thereon; finally, connecting these wires to the outside world. During packaging, the gold lead with thickness about only 10μm is used for the connection, so the metal wires of each layer (the width of multi metal layer is about only 0.1μm) must be first collected to the uppermost layer; then, converting the size to the bond pad of about 10μm; finally, using the wire bonder to perform the wire bonding, so the gold lead with thickness about only 10μm can be used to connect to the outside world.
 
❒ Yield rate of wafer
Yield rate of a wafer refers to the ratio of normal dies on a chip to the total number of dies. As shown in Fig. 1, there are totally 24 dies on a Si wafer. After testing, 18 dies can operate normally, and 6 dies are malfunctioned and marked “X” by the tester. So, the yield rate of this wafer is 75% (18/24). The yield rate of a foundry is related to the cleanness of clean room, quality of engineers and operators, and quality of machines. Generally, it is very difficult to maintain the yield rate above 80%. The yield rates of Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) and United Microelectronics Corp. (UMC) can be maintained above 95%, so the quality level of semiconductor fabrication plant operation in Taiwan is very high.
 
❒ Throughput of foundry
The throughput of a foundry means the number of wafers the foundry may produce per month, for example, 100 thousands of 12” wafer per month. During the high season, the market orders might demand 200 thousands of wafers per month, so the foundry must define the priority of the orders according to the importance level of customers and thus the foundry might schedule their orders to the next year and even the year after next year. However, during the low season, the market orders might demand only 50 thousands of wafers per month, then the foundry only needs to product 50 thousands of wafers per month, meaning that only 50% of machines in the foundry are operating as usual (the other 50% of machines are idle). Then, the capacity utilization of this foundry would be only 50%.

【Remark】The aforementioned contents have been appropriately simplified to be suitable for reading by the public, which might be slightly differentiated from the current industry situation. If you are the expert in this field and would like to give your opinions, please contact the writer. If you have any industrial and technical issues, please join the community for further discussion.